[Citation Statistics from Google Scholar]


* : advising/co-advising student

# : collaborator’s student

: collaborator in academia

: collaborator in industry

2015

Book Chapters:

123. Zhenhong Liu* and Nam Sung Kim. An ultra-low-power image signal processor for smart camera applications. CISS Research Series, Book 3: Smart Camera, Springer, 2015.

Competitively Reviewed Conference Papers with Archival Proceedings:

122. Sankaralingam Panneerselvam#, Michael M. Swift, and Nam Sung Kim. Bolt: Faster reconfiguration in operating systems. USENIX Annual Technical Conference (ATC), 6 pages, July 2015.

121.  David Palframan*, Nam Sung Kim, and Mikko Lipasti. COP: To compress and protect main memory. IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 12 pages, Jun 2015. Acceptance rate of regular papers is 19%.

120.  Amir Yazdanbakhash#, David Palframan*, Azadeh Davoodi, Nam Sung Kim, and Mikko Lipasti. Online and operand-aware detection of failures utilizing false alarm vectors. IEEE/ACM Great Lake Symp. on VLSI (GLSVLSI), Apr 2015.

119.  Richard Berger, Richard Ferguson, Addison Floyd*, and Nam Sung Kim. Next generation space processor study. Government Microcircuits Applications & Critical Technology (GOMACTech) Conference, Mar 2015.

118.  Young Hoon Son#, Sukhan Lee#, Seongil O#, Sanghyuk Kwon#, Nam Sung Kim, and Jung Ho Ahn. CiDRA: A Cache-inspired DRAM resilience architecture. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), Feb 2015. Acceptance rate is 22%.

117. Hao Wang*, Changjae Park, Gyungsu Byun, Jung Ho Ahn, and Nam Sung Kim. Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), Feb 2015. Acceptance rate is 22%.

116. Amin Farmahini-Farahani*, Katherine Morrow, Jung Ho Ahn, and Nam Sung Kim. NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), Feb 2015. Acceptance rate is 22%.

115.  David Palframan*, Nam Sung Kim, and Mikko Lipasti. iPatch: Intelligent fault patching to improve energy efficiency. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), Feb 2015. Acceptance rate is 22%.

Competitively Reviewed Journal Papers:

114. Mohammad Alian*, Daehoon Kim*, and Nam Sung Kim. pd-gem5: Simulation infrastructure for parallel/distributed computer systems, IEEE Computer Architecture Letters, in press.

113. Ismail Akturk#, Ulya Karpuzcu, and Nam Sung  Kim. Decoupling control and data processing for approximate near-threshold voltage computing. IEEE Micro, Jul-Aug 2015.

112. Heesung Lim, Taejoon Park, and Nam Sung Kim. Joint optimization of computational accuracy and algorithm parameters for energy-efficient recognition algorithms. IET Electronic Letters, in press.

2014

Competitively Reviewed Conference Papers with Archival Proceedings:

111.  Paula Aguilera*, Katherine Morrow, and Nam Sung Kim. Fair share: Allocation of GPU resources for both performance and fairness. IEEE Int. Conf. on Computer Design (ICCD), Oct 2014.

110.  Hamid Reza Ghasemi* and Nam Sung Kim. RCS: runtime resource and core scaling for power-constrained multi-core processors. ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), 12 pages, Aug 2014. Acceptance rate is 26%.

109. Hao Wang*, Ripudaman Singh*, and Nam Sung Kim. Memory scheduling towards high-throughput cooperative heterogeneous computing. ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), 12 pages, Aug 2014. Acceptance rate is 26%.

108.  Yanpei Liu*, Stark Draper, and Nam Sung Kim. SleepScale: Runtime joint speed scaling and sleep states management for power efficient data centers. IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 12 pages, Jun 2014. Acceptance rate of regular papers is 19%.

107. Young Hoon Son#, Seongil O#, Nam Sung Kim, and Jung Ho Ahn. Row-buffer decoupling: A case for low-latency DRAM microarchitecture. IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 12 pages, Jun 2014. Acceptance rate of regular papers is 19%.

106.  Hoyoung Kim, Soojung Ryu, Abhishek Sinkar*,and  Nam Sung Kim. Quantitative comparison of the power reduction techniques Samsung reconfigurable processor. IEEE Int. Symp. Circuits and Systems (ISCAS), Jun 2014.

105.  Amin Farmahini-Farahani*, Nam Sung Kim, and Katherine Morrow. Energy-efficient reconfigurable cache architectures for accelerator-enabled embedded systems. IEEE Int. Symp. on Perf. Analysis of Systems and Software (ISPASS), 10 pages, Apr 2014. Acceptance rate of regular papers is 33%.

104. Abhishek A. Sinkar*, Hao Wang*, and Nam Sung Kim. Maximizing throughput of power/thermal-constrained processors by balancing power consumption of cores. IEEE Int. Symp. on Quality Electronic Design (ISQED), 6 pages, Mar 2014.

103.  Ulya Karpuzcu, Ismail Akturk#, and Nam Sung Kim. Accordion: Toward soft near-threshold voltage computing. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2014. Acceptance rate of regular papers is 25%.

102.  David Palframan*, Nam Sung Kim, and Mikko Lipasti. Precision-aware soft error protection for GPUs. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2014. Acceptance rate of regular papers is 25%.

101.  Paula Aguilera*, Jungseob Lee*, Amin Farmahini Farahani*, Michael Schulte, Katherine Morrow and Nam Sung Kim. Variation-aware workload partitioning algorithms for GPUs supporting spatial multitasking. IEEE/ACM IEEE/ACM Design Automation and Test in European (DATE), 6 pages, Mar 2014.

100.  Paula Aguilera*, Katherine Morrow, Nam Sung Kim. QoS-aware dynamic resource allocation for spatial-multitasking GPUs. IEEE/ACM Asia South Pacific Design Automation Conf. (ASP-DAC), 6 pages, Jan 2014. Acceptance rate is 31%.

Competitively Reviewed Journal Papers:

113.  Dae Han  Ahn#, Nam Sung  Kim, Sang Jun  Moon, Taejoon  Park, and Sang Hyuk  Son. Optimization of a cell counting algorithm for mobile point-of-care testing platforms. Sensors, vol. 14, no. 8, Aug 2014.

98.     Syed Gilani*, Taejoon Park, and Nam Sung Kim.  Low-cost scratchpad memory organizations using heterogeneous cell sizes for low-voltage operations. Microprocessors and Microsystems, vol. 38, no. 7, Oct 2014.

97.     Srinivasan Narayanamoorthy*, Hadi Asghari Moghaddam*, Zhenhong Liu*, Taejoon Park, and Nam Sung Kim. Energy-efficient approximate multiplication for digital signal processing and classification applications. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. In press.

96.     Amin Farmahini*, Jung Ho Ahn, Katherine Morrow, and Nam Sung Kim. DRAMA: An architecture for accelerated processing near DRAM. IEEE Computer Architecture Letters (CAL). In press.

95.     Syed Gilani*, Nam Sung Kim, and Michael Schulte. Energy-efficient pixel arithmetic. IEEE Transactions on Computers, vol. 63, no. 8, Aug 2014.

94.     Nam Sung Kim, Taejoon Park, Srinivasan Narayanamoorthy*, and Hadi Moghaddam*. Multiplier supporting accuracy and energy trade-offs for recognition applications. IET Electronics Letters, vol. 50, no. 7, pp. 512-514, Mar, 2014.

2013

Competitively Reviewed Conference Papers with Archival Proceedings:

93.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latencies. IEEE/ACM Int. Symp. on Microarchitecture (MICRO), 12 pages, Dec 2013. Acceptance rate is 16%.

92.   Daniel Chang*, Younghoon Son#, Jung Ho Ahn, Hoyoung Kim, Minwook Ahn, Michael Schulte, and Nam Sung Kim. Dynamic bandwidth scaling for embedded DSPs with 3D-stacked DRAM and wide I/Os. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 8 pages, Nov 2013. Acceptance rate of regular papers is 26%.

91.   Hao Wang*, Abhishek A. Sinkar*, and Nam Sung Kim. Improving platform energy-chip area trade-off in near-threshold computing environment. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 8 pages, Nov 2013. Acceptance rate of regular papers is 26%.

90.   Vignyan Naresh#, Syed Gilani*, Erika Gunadi, Nam Sung Kim, Michael Schulte, and Mikko Lipasti. REEL: Reducing effective execution latency of floating point operation. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Sep 2013. Acceptance rate of regular papers is 23%.

89.   Amir Yazdanbakhsh#, David Palframan*, Azadeh Davoodi, Nam Sung Kim, Mikko Lipasti. Online and operand-aware detection of failures by utilizing false alarm vectors. IEEE Int. Workshop on Logic and Synthesis (IWLS), 6 pages, Jun 2013.

88.   Jingwen Leng#, Syed Gilani*, Ahmed El-Shafiey#, Tayler Hetherington#, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi. GPUWattch: Enabling energy optimizations in GPGPUs. IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 12 pages, Jun 2013. Acceptance rate is 19%.

87.   Yanpei Liu, Stark C. Draper, Nam Sung Kim. Queuing theoretic analysis of power-performance tradeoff in power-efficient computing. IEEE Conf. on Information Sciences and Systems (CISS), 8 pages, Mar 2013.

86.   Ulya Karpuzcu, Abhishek Sinkar*, Nam Sung Kim, and Josep Torrellas. EnergySmart: Toward energy-efficient manycores for near-threshold computing. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2013. Acceptance rate is 21%.

85.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Power-efficient computing for compute-intensive GPGPU applications. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2013. Acceptance rate is 21%.

84.   Daniel W. Chang*, Gyungsu Byun, Nam Sung Kim, and Michael J. Schulte. Reevaluating the latency claims of 3D stacked memories (a.k.a. 3D LIES: A 3D latency-based interconnect evaluation for stacked-memories). IEEE/ACM Asia South Pacific Design Automation Conf. (ASP-DAC), 6 pages, Jan 2013. Acceptance rate is 31%.

Competitively Reviewed Journal Papers:

83.   Ulya Karpuzcu, Nam Sung Kim, and Josep Torrellas. Coping with the higher susceptibility to parametric variation at near-threshold voltages. IEEE Micro, vol. 33, no. 4, pp. 6-14, Jul/Aug, 2013.

82.   David Palframan*, Nam Sung Kim, and Mikko Lipasti. Resilient high-performance processors with spare RIBs. IEEE Micro, vol. 33, no. 4, pp. 26-34, Jul/Aug, 2013.

81.   Hao Wang* and Nam Sung Kim. Improving throughput of many-core processors based on unreliable emerging devices under power constraint. IEEE Micro, vol. 33, no. 4, pp. 16-24, Jul/Aug, 2013.

80.   Abhishek Sinkar*, Hamid Reza Ghasemi*, Ulya Karpuzcu, Michael Schulte, and Nam Sung Kim. Low-cost per-core voltage domain support for power-constrained high-performance processors. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 22, no. 4, pp. 747-758, 2013.

79.   Alaa R. Alameldeen, Nam Sung Kim, Samira M. Khan, Hamid Reza Ghasemi*, Chris Wilkerson, Jaydeep Kulkarni, and Daniel A. Jiménez. Improving memory reliability, power and performance using mixed-cell designs. Intel Technology Journal, 2013.

78.   Abhishek Sinkar* Taejoon Park, Nam Sung Kim. Clamping virtual supply voltage of power-gated circuits for active leakage reduction and gate-oxide reliability improvement. IEEE Transactions on Very Large Scale Integration (VLSI) Systems,  vol. 21, no. 3, pp. 580-584, Mar 2013.

Competitively Reviewed Workshop Papers with Archival Proceedings:

77.    Euijin Kwon#, Jae Young Jang#, Jae W. Lee, and Nam Sung Kim. Optimal power allocation for multiprogrammed workload on single-chip heterogeneous processors. Workshop on Energy Efficient Design (WEED) in conjunction with IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 2013.

2012

Competitively Reviewed Conference Papers with Archival Proceedings:

76.   Vijay Sathish*, Michael Schulte, and Nam Sung Kim. Lossless and lossy memory-link compression techniques for improving performance of memory-bound GPGPU workloads. ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), 10 pages, Sep 2012. Acceptance rate is 19%.

75.   Hao Wang*, Vijay Sathish*, Ripudaman Singh*, Michael Schulte, and Nam Sung Kim. Workload and power budget partitioning for single-chip heterogeneous processors. ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), 12 pages, Sep 2012. Acceptance rate is 19%.

74.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Power-efficient computing for compute-intensive GPGPU applications. ACM Int. Conf. on Parallel Architecture and Compilation Techniques (PACT), Sep 2012.

73.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Virtual floating-point units for low-power embedded processors. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), 8 pages, July 2012.

72.   Ardavan Pedram#, Andreas Gerstlauer, Robert A. van de Geijn, Syed Gilani*, Michael Schulte, and Nam Sung Kim. A linear algebra core design for efficient level-3 BLAS. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP), July 2012.

71.   David Palframan*, Nam Sung Kim, and Mikko Lipasti. Mitigating random variation with spare RIBs: Redundant intermediate bitslices. IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN), 10 pages, Jun 2012. Acceptance rate is 17%.

70.   Ulya Karpuzcu#, Krishna Kolluru*, Nam Sung Kim, and Josep Torrellas. VARIUS-NT: A microarchitectural model of process variation for near-threshold voltage computing,” IEEE/IFIP Int. Conf. on Dependable Systems and Networks (DSN), 12 pages, Jun 2012. Acceptance rate is 17%.

69.   Hamid Reza Ghasemi*, Abhishek Sinkar*, Michael Schulte, and Nam Sung Kim. Cost-effective power delivery to support per-core voltage domains for power-constrained processors. IEEE/ACM Design Automation Conf. (DAC), 6 pages, Jun 2012. Acceptance rate is 22% (164 / 741).

68.   Abhishek Sinkar*, Hao Wang*, and Nam Sung Kim. Workload-aware voltage regulator optimization for power efficient multi-core processors. IEEE/ACM Design Automation and Test in European (DATE), Mar 2012.

67.   Jacob T. Adriaens#, Katherine Compton, Nam Sung Kim, and Michael Schulte. The case for GPGPU spatial multitasking. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2012. Acceptance rate is 17% (36/210).

Competitively Reviewed Journal Papers:

66.   Jungseob Lee* and Nam Sung Kim. Analyzing potential throughput improvement of power- and thermal-constrained multicore processors by exploiting DVFS and PCPG. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 225-235, Feb 2012.

65.   Nam Sung Kim, Stark Draper, Shi-Ting Zhou*, Sumeet Katariya#, Hamid Reza Ghasemi*, and Taejoon Park. Analyzing the impact of joint optimization of cell size, redundancy, and ECC on low-voltage SRAM array total area. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no 12, pp. 2333- 2337, Dec 2012.

64.   Nam Sung Kim, Abhishek Sinkar*, Jun Seomun#, and Youngsoo Shin. Maximizing frequency and yield of power-constrained designs using programmable power-gating. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 20, no 10, pp. 1885-1890, Oct 2012.

2011

Competitively Reviewed Conference Papers with Archival Proceedings:

63.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Energy-efficient floating-point arithmetic for low-power digital signal processors. IEEE Asilomar Conf. on Signals Systems, and Computers, 6 pages, Nov 2011.

62.   Jungseob Lee*, Vijay Satish*, Katherine Compton, Michael Schulte, and Nam Sung Kim. Improving the throughput of power-constrained GPUs using dynamic voltage/frequency and core scaling. ACM Int. Conf. on Parallel Architectures and Compilation Techniques (PACT), 10 pages, Oct 2011. Acceptance rate is 16% (36/221)

61.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Energy-efficient floating-point arithmetic for software-defined radio architectures. IEEE Int. Conf. on Application-specific Systems, Architectures and Processors (ASAP’11), 8 pages, Sep 2011. Acceptance rate is 26% (23/87)

60.   Jungseob Lee*, Vijay Satish*, Katherine Compton, Michael Schulte, and Nam Sung Kim. Workload-aware throughput optimization of power-constrained GPGPUs. Semiconductor Research Corporation (SRC) Technical Conf. (TECHCON), Sep 2011. This conference is only open to the SRC member companies and institutions.

59.   Jacob T. Adriaens#, Katherine Compton, Nam Sung Kim, Michael Schulte. The Case for GPGPU spatial multitasking. Semiconductor Research Corporation (SRC) Technical Conf. (TECHCON), Sep 2011. This conference is only open to the SRC member companies and institutions.

58.   Daniel Chang*, Nam Sung Kim, and Michael Schulte. Analyzing the performance and energy impact of 3D memory integration on embedded DSPs. IEEE Int. Conf. on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XI), 8 pages, Jul 2011.

57.   Jungseob Lee*, Paritosh Ajgaonkar*, and Nam Sung Kim. “Analyzing throughput of GPGPUs exploiting within-die core-to-core frequency variation. IEEE Int. Symp. on Perf. Analysis of Systems and Software (ISPASS), 10 pages, Apr 2011.

56.   Krishna Bharath*, Chunhua Yao#, Nam Sung Kim, Parmesh Ramanathan, and Kewal Saluja. A low cost approach to calibrate on-chip temperature sensors. IEEE Int. Symp. on Quality Electronic Design (ISQED), Mar 2011.

55.   Syed Gilani*, Nam Sung Kim, and Michael Schulte. Scratchpad memory optimizations for digital signal processing applications. IEEE/ACM Design Automation and Test in European (DATE), 6 pages, Mar 2011. Acceptance rate is 25% (191 of 781 submissions).

54.   David Palframan*, Nam Sung Kim, and Mikko Lipasti. Time-redundant parity for transient fault detection in combinational circuits. IEEE/ACM Design Automation and Test in European (DATE), 6 pages, Mar 2011. Acceptance rate is 25% (191 of 781 submissions).

53.   Hamid Reza Ghasemi*, Stark Draper, and Nam Sung Kim. Low-voltage on-chip cache architecture using heterogeneous cell sizes for multi-core processors. IEEE/ACM Int. Symp. on High-Performance Computer Architecture (HPCA), 12 pages, Feb 2011. Acceptance rate is 18% (42/227).

52.   Abhishek Sinkar* and Nam Sung Kim. AVS-aware power-gate sizing for maximum performance and power efficiency of power-constrained processors. IEEE/ACM Asia South Pacific Design Automation Conf. (ASP-DAC), 6 pages, Jan 2011. Acceptance rate is 33% (104/300).

Competitively Reviewed Workshop Papers:

51.   David Palframan*, Nam Sung Kim, and Mikko Lipasti. Spare RIBs: Redundant intermediate bitslices. Workshop on Resilient Architectures (WRA) in conjunction with IEEE/ACM Int. Symp. on Microarchitecture (MICRO), 6 pages, Dec 2011.

Competitively Reviewed Conference Poster:

50.   Jungseob Lee*, Vijay Satish*, Katherine Compton, Michael Schulte, and Nam Sung Kim. Workload-aware throughput optimization of power-constrained GPGPUs. IEEE/ACM Design Automation Conf. (DAC), Jun 2011. Acceptance rate including both regular and poster papers is 33% ((156+77)/690)

2010

Competitively Reviewed Conference Papers with Archival Proceedings:

49.   Erika Gunadi#, Abhishek Sinkar*, Nam Sung Kim, and Mikko Lipasti. Combating aging with the COLT duty cycle equalizer. IEEE/ACM Int. Symp. on Microarchitecture (MICRO), 12 pages, Dec 2010. Acceptance rate was 17% (42/248).

48.   Danbee Park#, Jungseob Lee*, Nam Sung Kim, and Taewhan Kim. Optimal Algorithm for Profile-Based Power-Gating: A Compiler Technique for Reducing Leakage on Execution Units in Microprocessors. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD’10), Nov 2010. Acceptance rate was 30% (108/360).

47.   Shi-Ting Zhou*, Sumeet Katariya#, Hamid Ghasemi*, Stark Draper, and Nam Sung Kim. Minimizing total area of low-voltage SRAM arrays through joint optimization of cell size, redundancy, and ECC. IEEE Int. Conf. on Computer Design (ICCD), 6 pages, Oct 2010. Acceptance rate was 29% (79/267).

46.   Jungseob Lee*, Eric Wang#, Hamid Ghasemi*, Lloyd Bircher, Yu Cao, and Nam Sung Kim. Workload-adaptive process tuning strategy for power-efficient multi-core processors. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2010. Acceptance rate was 34% (69/203).

45.   Abhishek Sinkar* and Nam Sung Kim. Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits. IEEE Int. Symp. on Quality Electronic Design (ISQED), 6 pages, Mar 2010. Acceptance rate was 31% (84/270).

44.   Dong-Keun Oh*, Nam Sung Kim, Charlie Chen, and Yu-Hen Hu. The compatibility analysis of thread migration and DVFS in multi-core processor. IEEE Int. Symp. on Quality Electronic Design (ISQED), 6 pages, Mar 2010. Acceptance rate was 31% (84/270).

43.   Jungseob Lee*, Shi-Ting Zhou*, and Nam Sung Kim. Analyzing impact of multiple ABB and AVS domains on throughput of power and thermal-constrained multi-core processors. IEEE/ACM Asia South Pacific Design Automation Conf. (ASP-DAC), 6 pages, Jan 2010. Acceptance rate was 33% (115/340).

42.   Dong-Keun Oh*, Nam Sung Kim, Charlie Chung Ping Chen, Yu-Hen Hu, and Azadeh Davoodi. Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors. IEEE/ACM Asia South Pacific Design Automation Conf. (ASP-DAC), 6 pages,  Jan 2010. Acceptance rate was 33% (115/340).

2009

Competitively Reviewed Conference Papers with Archival Proceedings:

41.   Abhishek Sinkar* and Nam Sung Kim. Analyzing potential total power reduction with adaptive voltage positioning optimized for multicore processors. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2009. Acceptance rate was 24% (52/210).

40.   Jungseob Lee* and Nam Sung Kim. Optimizing total power of many-core processor considering supply voltage scaling limit and process variations. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2009. Acceptance rate was 24% (52/210).  

39.   Mike Anderson#, Azadeh Davoodi, Abhishek Sinkar*, Jungseob Lee*, and Nam Sung Kim. Statistical static timing analysis considering leakage variability in power-gated design. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2009. Acceptance rate was 24% (52/210).

38.   Nam Sung Kim, Jun Seomun#, Abhishek Sinkar*, Jungseob Lee*, Tae Hee Han, Ken Choi, and Youngsoo Shin. Frequency and yield optimizations in power-constrained designs. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2009. Acceptance rate was 24% (52/210).

37.   Jungseob Lee* and Nam Sung Kim. Throughput analysis and optimization of power and thermal constrained multicore processors. IEEE/ACM Design Automation Conf. (DAC), Jul 2009. Acceptance rate is 22% (148/682).

Competitively Reviewed Workshop Papers:

36.   Nam Sung Kim. Power-efficient computing through approximations and morphic primitives for future teraflops workloads. Workshop on New Directions in Computer Architecture (NDCA) in conjunction with the 2009 Int. Symp. on Microarchitecture (MICRO), Dec 2009.

Competitively Reviewed Journal Papers:

35.   DiaaEldin Khalil#, Muhammad Khellah, Nam Sung Kim, Yehea Ismail, Tanay Karnik and Vivek De. SRAM dynamic stability estimation using MPFP and its applications. Microelectronics Journal, vol. 40, no. 11, pp. 1523-1530, Nov 2009.

34.   Muhammad Khellah, Nam Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Gunjan Pandya, Fatih Hamzaoglu, Tom Coan, Yih Wang, Kevin Zhang, Clair Webb, and Vivek De. Process, temperature, and supply-noise tolerant 45nm dense cache arrays with diffusion-notch-free (DNF) 6T SRAM cells and dynamic Multi-Vcc circuits. IEEE Journal of Solid State Circuits (JSSC), vol 44, no. 4, pp.1199-1208, Apr 2009.

33.   Keith Bowman, James Tschanz, Nam Sung Kim, Janice Lee, Chris Wilkerson, Shih-Lien L. Lu, Tanay Karnik, and Vivek De. Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance. IEEE Journal of Solid State Circuits (JSSC), vol. 44, no. 1, pp. 49-63, Jan 2009.

Book Chapters:

32.   Dongkeun Oh*, Nam Sung Kim, Charlie Chung Ping Chen, and Yu Hen Hu. A mathematical method for VLSI thermal simulation at the system and circuit-levels.  Recent Advancements in Modeling of Semiconductor Processes, Circuits and Chip-Level Interactions (Rasit Onur Topaloglu, Peng Li eds.), Bentham Publishing (www.ebook-engineering.org), 2009.

2008

Competitively Reviewed Conference Papers with Archival Proceedings:

31.   Muhammad Khellah, Nam Sung Kim, Yibin Ye, Dinesh Somasekhar, Tanay Karnik, Nitin Borkar, Fatih Hamzaoglu, Tim Coan, Yih Wang, Kevin Zhang, Clair Webb, and Vivek De. PVT-variations and supply-noise tolerant 45nm dense cache arrays with diffusion-notch-free (DNF) 6T SRAM cells and dynamic multi-Vcc circuits,” IEEE VLSI Circuit Symp., Jun 2008.

30.   Keith Bowman, James Tschanz, Nam Sung Kim, Janice Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, and Vivek K. De. Energy-efficient & metastability-immune timing-error detection and instruction replay-based recovery circuits for dynamic variation tolerance. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb 2008.

Competitively Reviewed Journal Papers:

29.   Diaa Khalil#, Muhammad Khellah, Nam Sung Kim, Yehea Ismail, Tanay Karnik, and Vivek De. Accurate estimation of SRAM dynamic stability. IEEE Transactions on Very Large Integration (VLSI) Systems, vol. 16, no. 12, pp. 1639-1647, Dec 2008.

28.   David Roberts#, Nam Sung Kim and Trevor Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. Microprocessors and Microsystems, vol. 32, no. 5-6, pp. 244-253, Aug 2008.

Invited Papers:

27.   Keith Bowman, James Tschanz, Nam Sung Kim, Janice Lee, Chris Wilkerson, Shih.-Lien. Lu, Tanay Karnik, and Vivek De. Energy-efficient and metastability-immune timing-error detection and recovery circuits for dynamic variation tolerance. IEEE Int. Conf. on Integrated Circuit Design and Technology (ICICDT), 2008.

2007

Competitively Reviewed Conference Papers with Archival Proceedings:

26.   DiaaEldin Khalil, Muhammad Khellah, Nam-Sung Kim, Yehea Ismail, Tanay Karnik, and Vivek De. SRAM dynamic stability estimation using MPFP. IEEE Int. Conf. on Microelectronics  (ICM), Dec 2007.

25.   Gregory Chen, David Blaauw, Trevor Mudge, Dennis Sylvester, and Nam Sung Kim. Yield-driven near-threshold SRAM design. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 6 pages, Nov 2007.

24.   David Roberts, Nam Sung Kim and Trevor Mudge. On-chip cache device scaling limits and effective fault repair techniques in future nanoscale technology. IEEE Euro Micro Conf. on Digital System Design (DSD), 8 pages, Aug 2007.

23.   James Tschanz, Nam Sung Kim, et al. Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb 2007.

Competitively Reviewed Journal Papers:

22.   Muhammad Khellah, Dinesh Somasekhar, Yibin Ye,  Nam Sung Kim, Gunjan Pandya, Ali Farhang, Kevin Zhang, and Vivek De. A 256-Kb dual-VCC SRAM building block in 65-nm CMOS process with actively clamped sleep transistor. IEEE Journal of Solid State Circuits (JSSC), vol. 42, no. 1, pp. 233-207, Jan 2007.

2006

Competitively Reviewed Conference Papers:

21.   Muhammad Khellah, Yibin Ye, Nam Sung Kim, Dinesh Somasekhar, Gunjan Pandya, Ali Farhang, Kevin Zhang, and Vivek De. Wordline & bitline pulsing schemes for improving SRAM cell stability in low-Vcc 65nm CMOS designs. IEEE VLSI Circuit Symp., Jun 2006.

20.   Muhammad Khellah, Nam Sung Kim, Jason Howard, Greg Ruhl, Yibin Ye, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, and Vivek De. A 4.2Ghz, 130Mb/cm2, dual-Vcc SRAM in 65nm CMOS featuring active power management with autonomous compensation of PVT variation & aging impacts. IEEE Int. Solid-State Circuit Conf. (ISSCC), Feb 2006.

2005

Competitively Reviewed Conference Papers with Archival Proceedings:

19.   Nam Sung Kim, Vivek De, and Trevor Mudge. Total power-optimal pipelining and parallel processing under process variations in nanometer technology. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 6 pages, Nov 2005.

18.   Robert Bai, Nam Sung Kim, Dennis Sylvester, and Trevor Mudge. Total leakage optimization strategies for multi-level caches. IEEE/ACM Great Lake Symp. on VLSI (GLSVLSI), Apr 2005.

17.   Robert Bai, Nam Sung Kim, Dennis Sylvester, and Trevor Mudge. Power-performance trade-offs in nanometer scale multi-level caches considering total leakage power. IEEE/ACM Design Automation and Test in Europe (DATE), Mar 2005.

Competitively Reviewed Journal Papers:

16.   Nam Sung Kim, David Blaauw, and Trevor Mudge. Quantitative analysis and optimization techniques for on-chip cache leakage power. IEEE Transactions on Very Large Integration (VLSI) Systems (TVLSI), vol. 13, no. 10, pp. 1147-1156, Oct 2005.

2004

Competitively Reviewed Conference Papers with Archival Proceedings:

15.   Nam Sung Kim, Valeria Bertaco, Todd Austin, and Trevor Mudge. Microarchitectural power modeling technique for deep sub-micron processors. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2004.

14.   Nam Sung Kim and Trevor Mudge. Single-VDD and single-VT super-drowsy techniques for low-leakage high-performance instruction caches. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), Aug 2004.

Competitively Reviewed Journal Papers:

13.   [Top pick of Year 2004] Dan Ernst, Nam Sung Kim, et al. Razor: Circuit-level correction of timing errors for low-power operation. IEEE Micro, vol. 24, no. 6, pp. 10-20, Dec 2004.

12.   Nam Sung Kim, Kriszitan Flautner, David Blaauw, and Trevor Mudge. Circuit and microarchitectural techniques for reducing cache leakage power. IEEE Transactions on Very Large Integration (VLSI) Systems (TVLSI), vol. 12, no. 2, pp. 167-184, Feb 2004.

2003

Competitively Reviewed Conference Papers with Archival Proceedings:

11.   [Best Paper Award] Dan Ernst, Nam Sung Kim, et al. Razor: A low-power pipeline based on circuit-level timing speculation. IEEE/ACM Int. Symp. on Microarchitecture (MICRO), 12 pages, Dec 2003.

10.   Nam Sung Kim, David Blaauw, and Trevor Mudge. Leakage power optimization techniques for ultra deep sub-micron multi-level caches. IEEE/ACM Int. Conf. on Computer Aided Design (ICCAD), 6 pages, Nov 2003.

9.      Nam Sung Kim, Trevor Mudge, and Richard Brown. A 2.3Gb/s fully integrated and synthesizable Rijndael core. IEEE Custom Integrated Circuit Conf. (CICC), Sep 2003.

8.      Nam Sung Kim and Trevor Mudge. The microarchitecture for a low power register file. IEEE/ACM Int. Symp. on Low Power Electronic Design (ISLPED), 6 pages, Aug 2003.

7.      Nam Sun Kim and Trevor Mudge. Reducing register ports using delayed write-back queue and operand pre-fetch. ACM Int. Conf. on Supercomputing (ICS), 11 pages, Jun 2003.

Competitively Reviewed Journal Papers:

6.      [Cover Feature of Month] Nam Sung Kim, Todd Austin, David Blaauw, Trevor Mudge, Kriszitan Flautner,  Jie S. Hu, Mary Jane Irwin, Mahmut Kandemir, and Vijaykrishnan Narayanan, Leakage current — Moore’s Law meets static power. IEEE Computer, vol. 36, no. 12, pp. 68-75, Dec 2003.

2002

Competitively Reviewed Conference Papers with Archival Proceedings:

5.      Nam Sung Kim, Kriszitan Flautner, David Blaauw, and Trevor Mudge. Drowsy instruction caches – Reducing leakage power using dynamic voltage scaling and cache sub-bank prediction. IEEE/ACM Int. Symp. on Microarchitecture (MICRO), 12 pages, Nov 2002.

4.      Kriszitan Flautner, Nam Sung Kim, Steven Martin, David Blaauw, and Trevor Mudge. Drowsy Caches: Simple techniques for reducing leakage power. IEEE/ACM Int. Symp. on Computer Architecture (ISCA), 10 pages, May 2002.

Competitively Reviewed Workshop Papers:

3.      Nam Sung Kim, Todd Austin, and Trevor Mudge, Low-energy data cache using sign compression and cache line bisection. Annual Workshop on Memory Performance Issues (WMPI) in conjunction with Int. Symp. on Computer Architecture, May 2002.

2001

Book Chapters:

2.      Nam Sung Kim, Todd Austin, Trevor Mudge, and D. Grunwald. Challenges for architectural level power modeling in power aware computing (R. Melhem and R. Graybill eds.). Kluwer Academic Publishers: Boston, MA, 2001.

1998

Competitively Reviewed Conference Papers with Archival Proceedings:

1.  Namseung Kim, Hoon Choi, Seungjong Lee, Seungwang Lee, In-Cheol Park, Chong-Min Kyung. Virtual chip: making functional model work on real target systems. IEEE/ACM Design Automation Conf. (DAC), Jun 1998.